When displaying video signals on a fixed-matrix display device (e.g., a TFT display panel), the input video frequently needs to be reformatted in order to suit the display device. The horizontal blanking and/or the clock rate may need to be changed and the image might have to be re-sampled to adjust the line and pixel resolution whilst minimizing or even eliminating output line rate fluctuations. For low-cost applications this can be done using only a small, inexpensive, memory buffer holding only a few lines of video image. However, in this case the output video signal has to be accurately synchronized with the input video.
If the input video clock (digital video) or the synchronization frequency (analog signal) is stable relative to the output clock, the main problem that needs to be solved is maintaining the correct delay (called phase-offset) between the vertical synchronization in input and output. The correct delay depends on the re-formatting being performed. The output of image data in each output frame needs to start just the right amount of time after the first input image data is captured so that the memory buffer, also known as decoupling memory buffer, is pre-filled with the right amount of image data: not so much that it later overflows and not so little that it later runs empty. A fine-tuning feedback control of the clock or frame layout is required because constraints on the frame geometry imposed by the display device or the clocking precision make it impossible to exactly match input and output frame timings and/or to avoid a gradual drift due to temperature variation and so forth.
The obvious and well-known method to maintain a fixed vertical synchronization phase offset is to implement a phase-locked loop that regulates the output clock to maintain the selected target phase offset between input and output vertical synchronization. The respective vertical phase-locked loop may be solely responsible for the output video clock (output frame rate) or it may act as a fine-tuning regulator on a free-running clock or a clock line-locked to the input horizontal synchronization signal. This method requires relatively precise calculations in hardware.
Another method is proposed in the U.S. Pat. No. 6,353,459. According to this US patent, a phase offset between input and output vertical synchronization is achieved in that the output of a buffer memory is simply triggered if a certain threshold level in the buffer memory is reached. That is, the output for a frame commences when a memory buffer threshold level is reached. Such a solution is not flexible at all and a respective implementation is not able to cope with the different situations that might occur when handling video streams in a computer (PC) environment or in a television (TV) application, for instance. Furthermore, many of the modern flat-panel displays are not able to cope with the video signals output by a system being based on the teaching of this US patent. It is an object of the present invention to provide an alternative and more efficient scheme for the synchronization and/or re-formatting of video signals.
It is an object of the present invention to provide a scheme for the synchronization and/or re-formatting of video signals that requires minimal memory buffering.